New Wafers For 3-D Transistors. In May last year, Intel shook up the chip industry when it debuted the first chips bearing 3-D transistors.
The other major chipmakers would like to make the same switch, but they're years away from doing so. Now wafer manufacturer Soitec hopes to help them along. On Monday, the firm announced it aims to produce wafers with a structure that could let fabs build 3-D transistors (often called FinFETs) in fewer steps than are needed to create the transistors on an ordinary wafer. It's a somewhat unexpected move. A stacked memory device on logic 3D technology for ultra-high-density data storage - Abstract - Nanotechnology. The switching location of a bipolar memristor: chemical, thermal and structural mapping - Abstract - Nanotechnology. Index of /~tking/stuff.
New Wafers For 3-D Transistors. In May last year, Intel shook up the chip industry when it debuted the first chips bearing 3-D transistors.
The other major chipmakers would like to make the same switch, but they're years away from doing so. Now wafer manufacturer Soitec hopes to help them along. On Monday, the firm announced it aims to produce wafers with a structure that could let fabs build 3-D transistors (often called FinFETs) in fewer steps than are needed to create the transistors on an ordinary wafer. It's a somewhat unexpected move. For a few years now, the Bernin, France-headquartered company has been perfecting a way to build wafers for the FinFET's main competitor: the ultrathin body silicon-on-insulator or fully depleted SOI transistor. These 2-D-optimized wafers are already pretty far along.
But Soitec envisions its wafers will be useful for more than just extending the life of planar transistors. Selling chipmakers on more expensive wafers might take some time. (Image: IBM) Transistor Wars. Another key stumbling block for UTB SOI adoption is the supply chain.
At the moment, there are few potential providers of ultrathin SOI wafers, which could ultimately make manufacturers of UTB SOI chips dependent on a handful of sources. Intel's Mark Bohr says the hard-to-find wafers could add 10 percent to the cost of a finished wafer, compared to 2 to 3 percent for wafers bearing 3-D transistors (an estimate from the SOI Industry Consortium suggests that finished UTB SOI wafers will actually be less expensive). UMC Wins Qualcomm 28nm Second Source Contract! This is common knowledge in Taiwan but apparently the guys over at SemiAccurate.com did not get the memo.
I hear a name change is in the works: www.RarelyAccurate.com. Remember, these are the same clairvoyants who said TSMC shut down 28nm which as we now know is absolutely false. The QCOM elite stay at the Hsinchu Royal Hotel which is 5 minutes away from UMC HQ. The Royal is also my hangout so I see and hear these guys quite a bit. TSMC absolutely did NOT halt 28nm production! This article is titled “UMC Wins Qualcomm’s 28nm Node Contract” but what they mean is second source contract. If you look through the UMC 2010 annual report you will see that UMC has a handful of customers that do the bulk of the business. Does TSMC enjoy doing all of the bleeding edge work only to get shut out when serious production starts? TSMC 28nm Yield Explained! One thing you have to understand is that the Fabless - Foundry relationship is hugely contractual. The Truth of TSMC 28nm Yield! InShare53. Intel exec says fabless model “collapsing” PUB08-154-NEP-024.pdf.
Openings. PhD Student Position in Nanoelectronics PhD student positions are available at the Laboratory of Nanoscale Electronics and Structures at EPFL (Lausanne, Switzerland) headed by Prof.
Andras Kis. Highly motivated students will have an opportunity to work on projects related to novel nanoelectronic devices based on 2D materials as well as nanomaterial growth. The group employs AFM, transport measurements in a cryostat with a magnet and related techniques for measurements on nanoscale structures we fabricate in the EPFL class 100 cleanroom. Requirements include a Master's degree in physics, electrical engineering or materials science. Candidates are invited to send a CV (as a pdf or rtf attachment only) including a brief description of research experience, statement of research interest and the contact information for three references by e-mail to job.lanes@epfl.ch.
For more information on EPFL, please visit Postdoc position We are continuosly looking for highly qualified postdoc candidates. Nuo Xu. Semiconductor Manufacturing & Design: covering the technology and business issues in manufacturing and designing semiconductors. Semiconductors News & Articles.