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PCI Express

PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has numerous improvements over the aforementioned bus standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance-scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting (AER)[1]), and native hot-plug functionality. More recent revisions of the PCIe standard support hardware I/O virtualization. The PCIe electrical interface is also used in a variety of other standards, most notably ExpressCard, a laptop expansion card interface. Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the conventional PCI specifications. Architecture[edit] A full-height 4x PCIe card. Related:  Gadgets

Differential signaling Elimination of noise by using differential signaling. Advantages[edit] Tolerance of ground offsets[edit] In a system with a differential receiver, desired signals add and noise is subtracted away. Suitability for use with low-voltage electronics[edit] In the electronics industry, and particularly in portable and mobile devices, there is a continuing tendency to lower the supply voltage in order to save power and reduce unwanted emitted radiation. To see why, consider a single-ended digital system with supply voltage . and the low logic level is 0 V. . and the other at 0 V, is . . . Resistance to electromagnetic interference[edit] This advantage is not directly due to differential signaling itself, but to the common practice of transmitting differential signals on balanced lines.[1][2] Single-ended signals are still resistant to interference if the lines are balanced and terminated by a differential amplifier. Comparison with single-ended signaling[edit] Uses[edit] Differential pairs include:

Conventional PCI Conventional PCI, often shortened to just PCI, is a local computer bus for attaching hardware devices in a computer. PCI is an initialism of Peripheral Component Interconnect and is [2] part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any particular processor's native bus. Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the processor's address space.[3][page needed] It is a parallel bus, synchronous to a single bus clock. Attached devices can take either the form of an integrated circuit fitted onto the motherboard itself (called a planar device in the PCI specification) or an expansion card that fits into a slot. History[edit] A typical 32-bit, 5 V-only PCI card, in this case, a SCSI adapter from Adaptec. A motherboard with two 32-bit PCI slots and two sizes of PCI Express slots Auto configuration[edit] Notes:

RAMCloud - RAMCloud Project - Confluence What is RAMCloud? RAMCloud is a new class of storage for large-scale datacenter applications. It is a key-value store that keeps all data in DRAM at all times (it is not a cache like memcached). From a practical standpoint, RAMCloud enables a new class of applications that manipulate large data sets very intensively. RAMCloud is also interesting from a research standpoint. The RAMCloud project is based in the Department of Computer Science at Stanford University. Learning About RAMCloud General information about RAMCloud, such as talks and papers. Introductory talk on RAMCloud by John Ousterhout, given at LinkedIn on October 12, 2011.The Case for RAMCloud: an early position paper that discusses the motivation for RAMCloud, the new kinds of applications it may enable, and some of the research issues that will have to be addressed to create a working system. How to Deploy and Use RAMCloud RAMCloud Performance Information for RAMCloud Developers The RAMCloud Test Cluster New Cluster Design Notes

Serial Peripheral Interface Bus SPI bus: single master and single slave Interface[edit] The MOSI/MISO convention requires that SDI on the master be connected to SDO on the slave, and vice versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise. SPI port pin names for particular IC products may differ from those depicted in these illustrations. The master does not use an addressing concept while communicating with the slave. Operation[edit] The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Most slave devices have tri-state outputs so their MISO signal becomes high impedance (logically disconnected) when the device is not selected. Data transmission[edit] To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports.

org-How to Install Front USB Ports Setup Front USB Install USB 2.0 Guide Connect Front USB to Motherboard Help Troubleshoot By Lee Penrod Copyright (C) 2003-2010 Directron.com. The following advice is based on years of experience. It is provided as a free service to our customers and visitors. However, Directron.com is not responsible for any damage as a result of following any of this advice. You are welcome to distribute these tips free to your friends and associates as long as it's not for commercial purposes. You are permitted and encouraged to create links to this page from your own web site. Introduction Front mounted USB is a fairly old concept, but it has been one that has been tricky for most people to hook up. Pass thru front USB Pass thru front USB works by having the ports on the front of the case connect to either a standard USB cable, or a fairly small rounded cable. Many 3rd party devices that add front USB to a system use the pass thru system. Front USB via a Port to Header connection Almost all motherboards these days have a USB header. Understanding the wires Common USB case header connectors

Current mode logic Current-mode logic is also an alternate name for Emitter-coupled logic. Current mode logic (CML), or source-coupled logic (SCL), is a differential digital logic family intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standard printed circuit boards.[1] CML termination scheme The transmission is point-to-point, unidirectional, and is usually terminated at the destination with 50 Ω resistors to Vcc on both differential lines. CML is frequently used in interfaces to fiber optic components. CML signals have also been found useful for connections between modules. This technology has widely been used in design of high-speed integrated systems, such as in telecommunication systems (serial data transceivers, frequency synthesizers, etc.). Applications in ultra low power: Recently, CML topology has been used in ultra-low power applications. See also[edit] References[edit]

Serial ATA Serial ATA (SATA) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA replaces the older AT Attachment standard (later referred to as Parallel ATA or PATA), offering several advantages over the older interface: reduced cable size and cost (seven conductors instead of 40), native hot swapping, faster data transfer through higher signalling rates, and more efficient transfer through an (optional) I/O queuing protocol. SATA host adapters and devices communicate via a high-speed serial cable over two pairs of conductors. SATA has replaced parallel ATA in consumer desktop and laptop computers, and has largely replaced PATA in new embedded applications. Serial ATA industry compatibility specifications originate from The Serial ATA International Organization (aka SATA-IO). Features[edit] SATA 6 Gbit/s controller (Marvell chipset), a PCI Express x1 card Hotplug[edit] Advanced Host Controller Interface[edit]

Enterprise PCIe SSD Does PCIe replace SATA and SAS SSDs? Not exactly. PCIe is a high-performance interface with performance targets of 415,000 IOPS and 2 GB/s of bandwidth. PCIe SSDs are intended to augment most server or storage systems by providing several hardware acceleration and caching capabilities to help boost performance. Performance targets vary per system and application. At Micron, we offer our customers choices—our complete SSD portfolio provides the best tool for the job. Is Micron a member of the SSD Small Form Factor Working Group? Yes. What is the secure erase password for the P320h SSD? ffff What type of NAND is used in the P320h drive? The P320h drive uses Micron’s SLC ONFI 2.1 NAND Flash. Can I reduce power consumption on a PCIe drive? Yes, you can reduce the drive’s power consumption to ≤25W by activating the power-limiting feature. In the command-line version (CLI) of RSSDM, perform these steps: The power-limiting feature also can be activated through the RSSDM GUI: Not exactly. No. No. Yes.

IEEE-488 IEEE-488 stacking connectors IEEE-488 is a short-range digital communications bus specification. It was created in the late 1960s for use with automated test equipment, and is still in use for that purpose. IEEE-488 was created as HP-IB (Hewlett-Packard Interface Bus), and is commonly called GPIB (General Purpose Interface Bus). It has been the subject of several standards. Origins[edit] In the late 1960s, Hewlett-Packard (HP)[1] was manufacturing various automated test and measurement instruments, such as digital multimeters and logic analyzers. HP licensed the HP-IB patents for a nominal fee to other manufacturers. Standards[edit] In 1975, the IEEE standardized the bus as Standard Digital Interface for Programmable Instrumentation, IEEE-488; it was revised in 1978 (producing IEEE-488-1978).[2] The standard was revised in 1987, and redesignated as IEEE-488.1 (IEEE-488.1-1987). In 1987, IEEE introduced Standard Codes, Formats, Protocols, and Common Commands, IEEE-488.2. Connectors[edit]

Outlook Web App | Steve Goodman's Tech Blog A great new feature in Windows Server 2012 R2 is Web Application Proxy. As part of my quest to find a supportable replacement for Hybrid Silent Redirection using TMG I’ve found Web Application Proxy may well be the solution to my problem. In my new two-part series on SearchExchange, we look at how to actually… If you’ve not yet heard, last month saw the release of Outlook Web App for iPhone and iPad. Less than a month after it’s release, the first update, version 1.0.1 is already out the door providing bug fixes and turning contact sync on by default. My latest SearchExchange.com article is now online. With Public Folders slowly, painfully making their way out from Exchange, you might find a need to replace shared calendars that traditionally you would have used a public folder for. With the recent release of Office 2011 for the Mac, Outlook makes a welcome return, spearheading the way toward full feature parity between Outlook on Windows and Mac.

Cyclic redundancy check A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. Blocks of data entering these systems get a short check value attached, based on the remainder of a polynomial division of their contents; on retrieval the calculation is repeated, and corrective action can be taken against presumed data corruption if the check values do not match. The CRC was invented by W. Wesley Peterson in 1961; the 32-bit CRC function of Ethernet and many other standards is the work of several researchers and was published during 1975. Introduction[edit] CRCs are based on the theory of cyclic error-correcting codes. A CRC is called an n-bit CRC when its check value is n bits. The simplest error-detection system, the parity bit, is in fact a trivial 1-bit CRC: it uses the generator polynomial x + 1 (two terms), and has the name CRC-1. Application[edit] CRCs and data integrity[edit] Computation of CRC[edit] , where

PCI-X It has been replaced in modern designs by the similar-sounding PCI Express (officially abbreviated as PCIe),[2] with a completely different connector and a very different logical design, being a single narrow but fast serial connection instead of a number of slower connections in parallel. History[edit] Background and motivation[edit] In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. PCI also suffered from the relative scarcity of unique interrupt lines. The lack of registered I/Os limited PCI to a maximum frequency of 66 MHz. Some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects could by themselves saturate the PCI bus's 133 MB/s bandwidth. PCI-X 1.0[edit] PCI-X 2.0[edit] In 2003, the PCI SIG ratified PCI-X 2.0. Technical description[edit] The two most fundamental changes are: Versions[edit]

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