u9621615. Serial Peripheral Interface Bus. SPI bus: single master and single slave Interface[edit] The MOSI/MISO convention requires that SDI on the master be connected to SDO on the slave, and vice versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise. SPI port pin names for particular IC products may differ from those depicted in these illustrations. The master does not use an addressing concept while communicating with the slave. Operation[edit] The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it.
Most slave devices have tri-state outputs so their MISO signal becomes high impedance (logically disconnected) when the device is not selected. Data transmission[edit] To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. MAX2077. Popular Electronics Detector Schematic. ESP15_US.