Loads of Linux Links: VHDL.
VHDL Books. VHDL samples. The sample VHDL code contained below is for tutorial purposes.
An expert may be bothered by some of the wording of the examples because this WEB page is intended for people just starting to learn the VHDL language. There is no intention of teaching logic design, synthesis or designing integrated circuits. It is hoped that people who become knowledgeable of VHDL will be able to develop better models and more rapidly meet whatever their objectives might be using VHDL simulations. Click here to have all references included, BIG! Contents A few VHDL compilers have bugs. Example of VHDL writing to standard output The VHDL source code is hello_world.vhdl This demonstrates the use of formatting text output to a screen. Example of VHDL reading and writing disk files The VHDL source code is file_io.vhdl This example is a skeleton for a VHDL simulation that needs input from a file, simulates based on the input and produces output to a file.
Simple parallel 8-bit sqrt using one component Other Links. VHDLDOC online manual. (up-to-date version always at : ( last change : $Date: 2001/03/09 17:39:42 $ ) Introduction VHDLDOC serves to create html documentaion of your vhdl-code.
It handles projects consisting of many files and libraries. The documentation is genrated by parsing your vhdl-code and formatting the comments you wrote into the code with a simple Mark-Up language. The package was developed by taking the kdoc-package from Sirtaj Singh Kang and then heavily modify it for the purpose of VHDL. If you have troubles or suggestions please contact Christoph.Schwick@cern.ch Generated Output The tool generates a set of html-pages.
The footer contains the info about the documentation generation. Installation If the package is not yet installed on your computer (check with which vhdldoc ) you can download the package here and install it yourself. Gunzip vhdldoc.tar.gz tar -xf vhdldoc.tar cd vhdldoc . where for [installalaltion-directory] you give the full directory-name where you want to install vhdldoc. Invocation. See the VHDL Language Reference Manual (VLRM) for Additional Details The following Mini-Reference can be divided into the following parts: I.
Primary Design Unit Model Structure A. Entity Declaration Format B. ArchitectureII. Each VHDL design unit comprises an "entity" declaration and one or more "architectures". Entity Declaration Format - Back To Top entity name is port( port definition list );-- input/output signal ports generic( generic list); -- optional generic list end name; Port declaration format: port_name: mode data_type; The mode of a port defines the directions of the singals on that pirt, and is one of: in, out, buffer, or inout.
Port Modes: An in port can be read but not updated within the module, carrying information into the module. An out port can be updated but not read within the module, carrying information out of the module. A buffer port likewise carries information out of a module, but can be both updated and read within the module. An inout port Example.