ASAM :: Information material.
JAVAPROCESSOR. SystemC. FSM. NOC. CORTESS-Tutorial-part5.pdf. DaRT Short Presentations and Demos. Sockets_socdesign.pdf. TTA-based Co-design Environment (TCE) | About Transport-Triggered Architectures. The TTA Principle Transport Triggered Architecture (TTA) is a processor design philosophy where the processors internal datapaths are exposed in the instruction set. All operation parameter reads and result writes are explicitly stated in the instruction set. TTA processor datapath consists of execution units, register files and buses that connect them. The processor is programmed by controlling directly the buses, and operations are executed as side-effect of these moves, by moving data to a specific trigger port of an function unit.
One operation typically consist of multiple moves, one for each operand and one for each result value. The instruction word for a TTA processor typically consists of a move slot for every datapath bus, so that every instruction word can contain multiple moves, one for each bus. Every instruction word can contain moves from multiple operations, so the instruction set states explicit instruction level parallelism, like VLIW processors. TTA Compared to VLIW. HAL - INRIA :: Accueil. ModEasy. 17th September 2007, Barcelona, Spain In conjunction with Forum on specification & Design Languages (FDL'07) The ModEasy'07 Workshop is organized in the scope of the ModEasy project. This project is intended to develop software tools and techniques to help the reliable design of embedded systems using advanced development and verification methodologies. These tools will be evaluated on automotive applications domain, such as reactive cruise control and anti-collision radar.
Areas of Interests Applications and algorithms for automotive domain Execution platform of automotive applications (FPGA, MPSoC, etc) Technology design related topics Workshop Program Two sessions are planned in the afternoon: First Session (Synthesis and Simulation) 15:00-15:30 Project Presentation (Prof. 16:30-16:50 Coffee Break 17:50-19:30 Open discussion and Workshop closure Workshop Proceedings We propose for all partners to prepare a short paper (4 pages) per presentation.
The Workshop proceedings can be found here. Benatitallah. DaRT Short Presentations and Demos. A detailed discussion of On-Chip Networks with Virtual Channels. CORTESS-Tutorial-part5. OCP-IP : White Papers Page. OCP-IP : Wheel Debug Page. Sockets_socdesign. SPIRIT+MARTE. OCP-IP_Debug_Working_Group_Whitepaper_3_26_2007.