Blue Pearl Software Inc.
Blue Pearl Software Inc. provides products that automate the generation of timing constraints, validate existing timing constraints and check functional design issues at the functional or register transfer level (RTL) of the digital chip design flow.
The Value of High Reliability RTL for FPGA Design - Blue Pearl Software Inc. John Molyneux, COO & Senior VP Sales and Marketing, Blue Pearl Software Introduction Today’s FPGA designs are typically developed by assembling between 50 to 100 unique IP blocks to form a complete System on Chip (SoC) including embedded processors, high speed serial interfaces, analog, signal processing and control logic.
These systems are large, complex and partitioned into multiple clock domains and reset structures required to interface and control the various subsystem and reduce overall system level power. FPGA designers, developing these advance SoCs, must not only develop functionally correct RTL, they must also meet conditions for downstream interoperability within the overall system. To reduce design risk and schedule slips, RTL code must be free of design errors, adhere to industry and corporate best practices, be free of dead code and unreachable finite state machine (FSM) states, in addition to having synchronized clock domains crossings to ensure metastability.
GreyCell WP. DO 254 Final. DO 254Video. Aerospace & Defense - Blue Pearl Software Inc. The Aerospace and Defense industry requires high-reliability electronics that operate in harsh conditions involving extremes in temperature, shock, vibration, moisture, dust, dirt and more.
Aerospace and Defense Engineers face a long list of challenges designing and verifying this mission critical technology, on time and to budget. Requirements for size, performance, and power are exasperated by compliance with rigorous safety and reliability standards – notably the DO-254 standard for assuring quality and safety for airborne electronic hardware. JumpStart - Blue Pearl Software Inc. The Blue Pearl JumpStart is a “build your own learning” program, included with the purchase of your new verification solution.
The JumpStart is tailor designed to give every user the foundational knowledge to be successful using the Visual Verification Suite to improve code quality, accelerate verification and decrease design risk. The JumpStart accelerates ramp up and adoption to ensure Hardware, IP and Verification engineers are productive from day one. The program reduces the impact to your design cycle time by minimizing “on project learning” and getting you back to maximum productivity sooner .
Events - Blue Pearl Software Inc. Blue Pearl Software Unveils JumpStart Training and Consulting - Blue Pearl Software Inc. Personalized JumpStart Services Ensure Out-of-the Box Productivity for ASIC, FPGA and IP RTL Verification SANTA CLARA, California – January 24, 2017 – Blue Pearl Software, Inc., a leading provider of Electronic Design Automation (EDA) software for ASIC, FPGA and IP design verification, today announced JumpStart training and consulting services.
The JumpStart solution is included with each purchase of the Visual Verification Suite and is personalized to match customers’ and partners’ unique training needs. Unlike traditional fee based tool training, the JumpStart training and consulting solution is included and tailored to provide every user the foundational knowledge to be successful using the Visuals Verification Suite on their design. With JumpStart, customers will see improved code quality, accelerated verification and decreased design risk by leveraging Blue Pearl experts on site or via long distance learning. Availability. Where Does RTL lint tool fit in my design flow? Working with ASIC and particularly FPGA designers, I’m frequently asked if finding bugs using existing simulation or emulation tools is sufficient.
The short answer is “Yes”,but it’s not always the most efficient. As design sizes increase but schedules do not expand to match, designers find themselves frustrated by spending too much time looking at simulation results or on bench testing to find bugs. Recently a mil aerospace customer lamented that, aside from enduring the process of re-planning and resetting schedules, and the risk of having a project cancelled for being 2+ weeks late, it’s very embarrassing to explain to management that the mistake turned out to be just some unconnected nets that could easily have been found by a lint tool in mere minutes. That is why customers now rely on lint or structural analysis tools like the Blue Pearl Software Suite in order to accelerate their IP and FPGA designs. Before Simulation –Blue Pearl can be used after initially writing the code. Blue Pearl Software Appoints John Molyneux President After Record Year - Blue Pearl Software Inc.
Company Positions Management Team for Continued Exponential Growth SANTA CLARA, California – January 16, 2017 – Blue Pearl Software, Inc., a leading provider of Electronic Design Automation (EDA) software for ASIC, FPGA and IP design verification, has promoted John Molyneux to the position of President of Blue Pearl Software.
“Molyneux’s leadership, experience and insight drove record sales during 2016. Blue Pearl more than doubled revenue while significantly increasing our installed base. This rapid growth and worldwide adoption of our Visual Verification Suite solution cumulated in Blue Pearl being named number 2 in the Best of EDA for 2016.” said CEO Ellis Smith. FPGA tools for more predictive needs in critical - Blue Pearl Software Inc. “Find bugs earlier.”
Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when? Structured development methodology was a breakthrough in computing, leading to the idea of structured programming and modular approaches to code. Systems engineers banished “goto” statements and embraced data flow diagrams, defining system inputs and outputs that can in turn be exploded into more detailed low-level functions with their inputs and outputs defined. The results of structured programming are rather spectacular. Those all sound like great things, especially for teams working on anything labeled “-critical”. In contrast, more modern agile methods can produce stunning results where requirements are more dynamic. Cross-viewing improves ASIC & FPGA debug efficiency - Blue Pearl Software Inc.
We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post.
As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is easier to use than other linting and CDC tools? An effective ASIC & FPGA design flow integrates analysis tools with the main EDA environment, minimizes jumping back and forth between tools, but allows flexibility in how results are obtained. In what Blue Pearl terms “continuous integration”, code review is automated to a manageable rule set so coding standards are enforceable across teams and projects.
While automated testing is fast and thorough, the key to productivity is how debug information is managed and resolved. The power of the Blue Pearl GUI is its cross-viewing capability. More powerful contextual capability is represented in several other windows. Tcl scripts and managing messages in ASIC & FPGA debug - Blue Pearl Software Inc. Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug.
Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects in the latest Blue Pearl 2016.1 release. An important aspect to regression testing is to run exactly the same tests as a design is iterated. The solution is scripting, automating the types and sequence of analysis with a saved file for execution. Tcl is a powerful scripting language popular in EDA circles, and rather than stay with their own syntax Blue Pearl has chosen to migrate their tools entirely onto Tcl. Both the GUI and the CLI are Tcl-based in the new release of the Blue Pearl suite. Those results are fundamentally a list of messages. Blue Pearl Software: Using the Management Dashboard in Viewer-only Mode. Blue Pearl Software Enters in to Agreement with FUJISOFT to Provide RTL Verification Solutions to Japan - Blue Pearl Software Inc.
Alliance accelerates ASIC and FPGA development, streamlining RTL verification, improving quality while eliminating metastability issues.
SANTA CLARA, California – Nov 15th, 2016 – Blue Pearl Software, Inc. a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced it has entered into an agreement with FUJISOFT, a global software technology company based in Yokohama, Japan, to provide RTL verification solutions including the next generation Visual Verification Suite in the Japanese market. The partnership highlights the continued growth of the Blue Pearl Software solutions in Asia. Electronic Design Tools. Blue Pearl Software Suite CDC Analysis and Viewer. Genesis of Blue Pearl Software.